Obtaining Process IDs
#include <sys/types.h>
#include <unistd.h>
pid_t getpid(void);
//return the pid of calling process
pid_t getppid(void);
//return the pid of its parent process (查看原文)
Circuit retiming changes the state representation for a system without changing its logical behavior. It is often used to balance the delays between different stages of a system. (查看原文)
This technique of guessing the branch direction and then initiating the fetching of instructions according to our guess is known as branch prediction. It is used in some form by virtually all processors. (查看原文)
Our technical presentation starts with a quick tour to show the relation between C, assembly code, and machine code. We then proceed to the details of IA32, starting with the representation and manipulation of data and the implementation of control. (查看原文)
A procedure call involves passing both data (in the form of procedure parameters and return values) and control from one part of a program to another. (查看原文)
Mispredicted branches can degrade the performance of a program considerably, thus motivating the use of conditional data transfer rather than conditional control transfer when possible. (查看原文)
One very general technique for avoiding hazards involves stalling, where the processor holds back one or more instructions in the pipeline until the hazard condition no longer holds. (查看原文)
This use of a stall to handle a load/use hazard is called a load interlock. Load interlocks combined with forwarding suffice to handle all possible forms of data hazards. Since only load interlocks reduce the pipeline throughput, we can nearly achieve our throughput goal of issuing one new instruction on every clock cycle. (查看原文)
Modern logic design involves writing textual representations of hardware designs in a hardware description language. The design can then be tested by both simulation and by a variety of formal verifications tools. Once we have confidence in the design, we can use logic synthesis tools to translate the design into actual logic circuits. (查看原文)
We can see that the conditions requiring special action by the pipeline control logic all cause our pipeline to fall short of the goal of issuing a new instruction on every clock cycle. (查看原文)
The memory system is organized as a hierarchy, with faster but smaller memories holding a subset of the memory being backed up by slower and larger memories. (查看原文)
Having the hardware invoke an operating system routine, which then returns control back to the hardware, allows the hardware and system software to cooperate in the handling of page faults. Since accessing a disk can require millions of clock cycles, the several thousand cycles of processing performed by the OS page fault handler has little impact on performance. (查看原文)
From the perspective of the processor, the combination of stalling to handle short-duration cache misses and exception handling to handle long-duration page faults takes care of any unpredictability in memory access times due to the structure of the memory hierarchy. (查看原文)
More recent processors support superscalar operation, meaning that they can achieve a CPI less than 1.0 by fetching, decoding, and executing multiple instructions in parallel. (查看原文)
